What is hdi pcb stackup? 2022 Best Guide

HDI is short for High Density Interconnect, PCB is Printed Circuit Board. So HDI PCB   is a high-density track layout in a smaller unit area (high-density routing). Hdi pcb stackup have been developed for many years.

The very first appeared in Japan and began mass production there in the 1990s and became an important type of printed circuit board. This is an advanced technology today. HDI is widely common in smart phones, tablets, Wi-Fi modules, Bluetooth devices and other high-end electronic products.

 Development stages of hdi pcb stackup

The first phase, from the development of IBM’s SLC in 1989 to the mid-1990s, was the heyday of HDI technology. Various technological processes are being studied. Mass production is not yet available.

In the second phase , from 1995 to 2005, Matsushita Electric and Toshiba successfully developed the HDI non-plating hole filling technology, which allows any inter-level connection to be realized; as well as laser drilling and the use of RCC prepreg as the dielectric layer are becoming the most important technical solution.

The third stage, from 2005 to 2010, at this stage, the production of multilayer boards became mass, IBIDEN published FVSS (Free Via Stacked up Structure) in ECWC 10, initiating hdi pcb stackup.

Stage four, 2010–present. The landmark mobile phone iPhone4 was released in 2010. It is the first mobile phone to use Anylayer electroplated hole design. It marks the beginning of the widespread adoption of Anylayer and has become the standard design for flagship mobile phones.

Types of hdi pcb stackup

1. By PCB processing technology: rank, 1, 2, 3, 4, etc.
2. According to the number of laser drillings, single laser drilling is rank 1, double laser drilling is rank 2, etc.
3. By the number of lamination cycles.
4. By finishing: electroplated gilding, organic protective coating, with immersion silver or tin, and others.

Stacking HDI boards

As a rule, hdi pcb stackup has the form 1+N+1, 2+N+2, 3+N+3, 4+N+4, where N is the number of layers of a multilayer core with non-blind holes, 1, 2, 3, 4 are pressing cycles layers with blind vias. For example, 10L 1 + N + 1, N for 8 layers without blind transition from L2 to L9, 1 for 1 type of blind pass, as shown in the picture below, micro vias L1-2, L2-9, L9 -10.

This article discusses the main options for layer stacks for four-layer boards.

The term hdi pcb stackup refers to the arrangement of copper and dielectric layers that make up the PCB. The stack we choose can play an important role in board performance in several different ways. For example, a good stack can lower the board’s ground impedance and limit radiation and crosstalk.

This article discusses the main stacks common in four-layer boards.

Stacks with power and ground layers

These two boards have the same layer order, but their thickness is different. This may seem like a minor modification, but we will see that appropriate spacing between different layers can improve board performance.

As you can see, both hdi pcb stackup signal layers are next to the polygon layers (either the ground polygon or the power polygon). Therefore, the reverse current of a given signal can flow through the adjacent layer.

This minimizes the inductance of the return current path by minimizing the area of ​​the loop created by current flow. The low inductance return path improves noise performance and reduces board radiation (both differential and common mode radiation).

Key factor in developing hdi pcb stackup

As a rule, the emission from a four-layer board can be 20 dB less than from the same circuit implemented on a two-layer board. The key factor here is to keep signals close to solid areas.

Therefore, to further improve noise and EMI performance, we can make the dielectric between the signal layer and the adjacent plane even thinner.

This simple trick gives us the improved stack shown in Figure 2, where the connection between the signal and polygon layers is increased by reducing the connection between the ground and power polygons.

hdi pcb stackup is Quite Popular

But this is not a serious disadvantage, because, in fact, neither of these two stacks provides sufficient communication between polygons. We will discuss this in more detail a little later. Note,

The hdi pcb stackup is widely common, but they have two drawbacks, both of which stem from the fact that the ground and power polygons are not close enough to each other, and therefore the interlayer capacitance between them is not large.

Disadvantages of common 4-layer stacks

The first problem with the stacks in Figures 1 and 2 occurs when the signal path transitions from layer 1 to layer 4, or vice versa.

If the signal frequency is high enough and the polygons are close together, reverse current can flow through the interlayer capacitance that exists between the ground and power polygons.

However, the absence of a direct conductive connection for the return current creates a discontinuity in the return path, and we can think of this discontinuity as a resistance between the planes.

Electric Field of hdi pcb stackup

If the interlayer capacitance is not large enough, the electric fields of hdi pcb stackup will spread over a relatively large area of ​​the board so that the impedance between the polygons decreases and the reverse current can flow back to the top polygon.

In this case, the fields created by this signal can interfere with the fields of neighboring signals, which also pass between layers. And this is not at all desirable. Unfortunately, on a 0.062″ (1.5748 mm) four-layer board, the polygons are far apart, and the capacitance between the polygons is small.

Consequently, we will have the mentioned interference from electric fields. This may not lead to signal integrity issues, but we will certainly create more EMI. That’s why when working with stacks,

Summary hdi pcb stackup

It is good practice to add a decoupling capacitor near the via to reduce the hdi pcb stackup impedance. However, such decoupling capacitors are not effective with very high frequency signals. It is due to the low natural resonant frequency.

For signals above about 200-300 MHz, we cannot rely on a decoupling capacitor to create a low impedance return path. Therefore, we need both a decoupling capacitor and a relatively large interlayer capacitance for higher frequencies.